(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit having a test function, and more particularly, to a semiconductor integrated circuit which can realize a minimum pulse width from a rising edge to a falling edge or from a falling edge to a rising edge of a pulse, which has been difficult to form in a testing device.
(2) Description of the Related Art
The prior art semiconductor integrated circuit of the kind to which the present invention relates is first explained to assist the understanding of the present invention. FIG. 1 is a circuit diagram showing such a prior art semiconductor integrated circuit device, and FIG. 2 is a timing chart referred to for describing the operation of the circuit shown in FIG. 1.
The prior art semiconductor integrated circuit device of the kind referred to above is disclosed, for example, in Japanese Patent Application Kokai Publication No. Sho 62-274276, and is used for forming a test clock signal having highly accurate time difference and pulse width in a high frequency operation.
With respect to a product such as a synchronous SRAM (Static Random Access Memory), in order to confirm the capability of master and slave switching in an internal latch circuit, it is necessary to transmit clocks of a very high frequency with accuracy to the inside of the semiconductor integrated circuit. However, an outer terminal of the semiconductor integrated circuit or a signal line between the semiconductor integrated circuit and a testing device inevitably has parasitic capacitance and distributed resistance. Therefore, it is considered difficult to transmit a clock signal of a high frequency directly to the inside of the semiconductor integrated circuit. This is so because, even when it is attempted to supply a clock signal of a high frequency, the time constant circuit formed by the above parasitic capacitance and distributed resistance causes a signal delay or a waveform distortion of the clock signal, that cannot be ignored.
In the system shown in FIG. 1, which is disclosed in Japanese Patent Application Kokai Publication No. Sho 62-274276, a system clock signal SCK which is supplied from an external terminal is supplied through an AND gate G11 to clock terminals of flip-flops FF1, FF2, etc. constituting an internal logic circuit. A control signal C which is also supplied from an external terminal, is a switching control signal for controlling the switching between the above-mentioned system clock signal SCK and a later explained clock signal TCK which is generated by a test clock signal TCK generator, and is supplied to an AND gate G12. An inverted output C' is supplied as a control signal to another input terminal of the AND gate circuit G11. A non-inverted output of the AND gate G12 is supplied as a control signal to an AND gate G13, which transmits the test clock signal TCK provided from the test clock signal TCK generator which is explained later. The AND gates G11 and G13 have their output terminals connected to a wired OR gate YG1 whose output signal is provided to the clock terminals of the above-mentioned flip-flops FF1, FF2, etc. The internal logic circuit comprises the flip-flop FF1 illustrated as an example, a logic block LOG for receiving the output thereof and an output signal from another flip-flop (not shown), and the flip-flop FF2 which receives an output signal of the logic block LOG.
In order to permit accurate determination of the signal propagation delay time in the logic block LOG in the internal logic circuit, generator circuits for generating following test clock signals TCK1 and TCK2 are provided.
A first test signal TCA externally supplied from a first terminal is supplied to an input buffer G14 constituted by an AND gate, and is also supplied to a delay inverter circuit DL constituted by three NAND gates G15, G16 and G17 having an inverter construction. The AND gate G14 and the NAND gate G17 have their output terminals connected to a wired AND gate YG2. The wired AND connection provides a one-shot pulse substantially corresponding to the delay time of the delay circuit DL in synchronization with the rising of the signal TCA from a low level (i.e., logic "0") to a high level (i.e., logic "1").
A second test signal TCB which is externally supplied from a second terminal, is supplied to a similar one-shot pulse generator. Specifically, the second test signal TCB is supplied to an input buffer G18 constituted by an AND gate, and is also supplied to a delay inverter circuit DL constituted by three serially connected NAND gates G19, G20 and G21 having an inverter construction. The AND gate G18 and the NAND gate G21 have their output terminals connected to a wired AND gate YG4. This wired AND connection forms a one-shot pulse substantially corresponding to the delay time of the delay inverter circuit DL in synchronization with the rising of the signal TCB from a low level (or logic "0") to a high level (or logic "1").
The above two one-shot pulse generators have their output terminals connected to a wired OR gate YG3 whose output forms the test clock signal TCK described above.
The operation of the test clock generator in this circuit will now be described with reference to a timing chart shown in FIG. 2.
When the test signal TCA is changed in its level from the low level to the high level, the output signal of the delay inverter circuit DL is changed in its level from the high level to the low level after a delay time. The clock signal TCK1 from the wired AND gate YG2 is thus at the high level during the delay time T15 of the delay inverter circuit DL, during which the two signals are at the high level. Likewise, when the second test signal TCB is changed from the low level to the high level, the output signal of the delay inverter circuit DL is changed in its level from the high level to the low level after a delay time. The clock signal TCK2 from the wired AND gate YG4 is thus at the high level during the delay time T15 of the delay inverter circuit DL, during which the two signals are at the high level.
The time difference T16 between the clock signals TCK1 and TCK2 thus can be derived or calculated from the rise time difference T14 between the two test signals TCA and TCB externally supplied from the external terminals. Since the clock signals TCK1 and TCK2 are generated by the internal circuit, the time difference between the rising edges of both the clock signals is substantially equal to the above time difference T14, and the pulse width is set by the delay time T15. Since the clock signals TCK1 and TCK2 are formed by the internal circuit, their pulse widths T15 and falling edges are respectively substantially constant. Thus, for accurate testing of a high frequency clock signal, it is only necessary that the time difference T14 between the rising edges of the test signals TCA and TCB externally supplied through the external terminals is accurate.
In the above prior art semiconductor integrated circuit, since the path of the system clock and the path of the test clock are different, the external input and internal timing cannot be accurately controlled.
In addition, since the one-shot pulse generators are utilized, it is impossible to vary the pulse width from the rising to the falling of the clock (hereinafter referred to TKHKL) and the pulse width from the falling to the rising of the clock (hereinafter referred to as TKLKH).
Furthermore, in the case where both TKHKL and TKLKH are measured, there is a problem that the circuit scale is increased.